(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating interconnect bumps of improved height and reliability.
(2) Description of the Prior Art
In the art of creating semiconductor devices, many mutually supporting technologies are used. While a considerable amount of attention is typically dedicated to the creation of the semiconductor device per se, these devices after their creation must be further connected to surrounding circuitry or to other semiconductor devices. For the connections that must be made to the semiconductor device itself, various techniques have been developed and are in current use. In order to be able to electrically interface with the die, points of interconnect must be provided on a surface of the die. This has led to a number of divergent approaches such as the creation of Ball Grid Array (BGA) devices, Land Grid Array (LGA) and Pin Grid Array (PGA) devices, Chip Scale Packaging (CSP) and Quad Flat Pack (QFP) devices. One of the salient developments is the creation of the flip chip which has a pattern or array of interconnect points spaced over the active surface of the die, the flip chip is mounted face-down to the surface of a substrate. The methods that are used to create the points of electrical interconnect on the surface of the flip essentially follows one of two approaches, that is the method whereby a solder bump is created and the method whereby a contact ball is created. Both methods start from a pad electrode that provides direct electrical interface with the die. In the method whereby a solder bump is created, a barrier layer is typically first blankly deposited over the surface of the wafer that contains the flip chip, the barrier layer typically comprising titanium or nickel or chromium, deposited using vacuum deposition methods or metal sputtering. After the barrier layer has been deposited, solder layers are selectively formed over the pad electrodes by methods of vacuum deposition or electrolytic plating or solder ball formation. For the method whereby a contact ball is created, ball bonding is performed over the surface of the pad electrodes by wire-bonding a (typically gold) wire to the pad electrode thus forming the contact ball.
In the formation of points of electrical contact on the surface of a semiconductor die, normal considerations of cost and reliability continue to play an important role. This places the method of forming solder bumps, the first of the two highlighted methods, at a disadvantage since this method requires the application of a barrier layer. Solder bump reliability further requires that the solder bump is of a reasonable sturdy construction, implying that the solder ball must have an adequate height from which follows that the vacuum deposition of the layer of solder (over the barrier layer) can become too time-consuming, further increasing the cost of using the solder bump method. The method of electrolytic plating that has been indicated above as being applicable for the formation of solder bumps does not lend itself to adequate control over the dimensional parameters of the solder bumps that are created. This is caused by the nature of the solder deposition of this method, whereby the deposition of the solder is heavily dependent on the energy (electric field distribution) that is applied for the formation of each solder bump while, since the solder bumps must be uniformly and simultaneously created for a large number of points of electrical contact, a common electrode is required to interconnect all contact pads over which solder bumps are to be created.
The ball bonding method has the disadvantage that each contact pad must be provided with a contact ball, placing a severe limitation on device throughput, making this method not suitable for high speed throughput and therefore for modern, cost effective production methods. In addition, since the method of contact ball formation depends on thermal treatment of interfacing surfaces, this method leads to poor reliability performance of the device and frequently leads to more sophisticated methods of contact ball creation which again add cost to the process.
The invention addresses these and other concerns by addressing issues of providing a solder bump of adequate height, the issue of missing solder bumps and the issue of the solder bump processing time or window.
U.S. Pat. No. 6,211,052 (Farnworth) shows a UBM and bump process using photoresist.
U.S. Pat. No. 5,904,156 (Advocate) shows a process for a dry film resist removal in the presence of electroplated bumps.
U.S. Pat. No. 5,914,274 (Yamaguchi) shows a substrate on which bumps are formed and a method of forming same.
U.S. Pat. No. 5,903,058 (Akram) shows a process for conductive bumps on a die.